Variable delay CMOS implementation for ultrasonic beamforming

An ultrasound imaging systems require high resolution and real-time processing. The real-time imaging can be achieved using a digital beamforming (DBF) method. One of the main important parts of the DBF is the real-time delay calculation. The design and implementation of a pipelined architecture for the beamforming delay calculation is addressed. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18 /spl mu/m technology and the resulting layout area is 0.5 mm/sup 2/, while a total power consumption of 20 mW.

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