0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications

This paper describes the impact of substrate resistivity on the key components of the radio frequency (RF) CMOS for the system on chip (SOC) applications. The comparison includes the transistor, inductor, capacitor, noise isolation, latch-up as well as the well-to-well isolation in a 0.1 /spl mu/m (physical gate length) CMOS technology.

[1]  J.C. Leete,et al.  A 2.4 GHz CMOS transceiver for Bluetooth , 2001, 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173).

[2]  T.S. Fiez,et al.  A scalable substrate noise coupling model for design of mixed-signal IC's , 2000, IEEE Journal of Solid-State Circuits.

[3]  T.H. Lee CMOS RF: no longer an oxymoron , 1997, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997.

[4]  K.K. O,et al.  A bond-pad structure for reducing effects of substrate resistance on LNA performance in a silicon bipolar technology , 1998, Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198).

[5]  T. Yoshimasu,et al.  Linearity and low-noise performance of SOI MOSFETs for RF applications , 2002 .

[6]  I. Chen,et al.  Shallow trench isolation for advanced ULSI CMOS technologies , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[7]  S. Wong,et al.  Physical modeling of spiral inductors on silicon , 2000 .

[8]  A. Amerasekera,et al.  A shallow trench isolation for sub-0.13 /spl mu/m CMOS technologies , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[9]  Wolfgang Fichtner,et al.  Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility , 2002 .