Triple patterning in 10nm node metal lithography

The local metallization layers of logic products are historically the densest layouts to lithographically pattern and are key drivers of product density (and therefore cost). Due to delays in extreme-UV (EUV) lithography and difficulties in applying other resolution-enhancement technologies (RETs)— such as double-patterning methods—triple-patterning technology (TPT) is a strong option for handling the local metal layers of the upcoming 10nm logic technology node ( 44–48nm minimum feature pitch). Several TPT methods, including ones developed by us, are being considered in different product areas of semiconductor manufacturing.1, 2 For advanced logic metal layers, the main TPT option assumes a process flow known as litho-etch-litho-etch-litho-etch (LELELE). In this flow, the final substrate pattern is the logical OR of three successive lithography+etch sequences, each sequence using a single traditional lithography exposure and a single etch step (see Figure 1). The use of LELELE TPT in a product design and production flow involves the following steps: design of TPT-compliant layout; design verification; decomposition of the layout into the three TPT single-exposure wafer targets (via TPT decomposition software); RET/optical proximity correction (OPC) steps for each single-exposure wafer target; OPC verification; mask data preparation; mask manufacture; and wafer processing in the fabrication facility (fab). There are many difficulties in achieving a high-yielding, cost-effective TPT process. Here, we first look at problems in mask manufacture and wafer production flow, especially cost, turn-around time, and the logistical challenges of tripling the number of mask and fab process steps per layer. However, the complexity and process control requirements of a TPT mask and wafer flow also increase substantially. Moreover, potential negative interactions can cause device failure between feature edge placements from the different litho-etch Figure 1. Examples of metal routing configuration in design and with double (DPT) and triple patterning technology (TPT), showing the potentially large benefit for pattern density of triple patterning for 1D features. The different colors of the polygon in the decomposed layouts represent the different mask target layouts (two masks for DPT, three masks for TPT).