AppSAT: Approximately deobfuscating integrated circuits
暂无分享,去创建一个
Meng Li | David Z. Pan | Yier Jin | Zheng Zhao | Kaveh Shamsi | Travis Meade | Meng Li | D. Pan | Zheng Zhao | Yier Jin | Kaveh Shamsi | Travis Meade
[1] Houman Homayoun,et al. Hybrid STT-CMOS designs for reverse-engineering prevention , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[2] Giorgio Di Natale,et al. A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).
[3] Jarrod A. Roy,et al. EPIC: Ending Piracy of Integrated Circuits , 2008, 2008 Design, Automation and Test in Europe.
[4] Takeshi Fujino,et al. Diffusion Programmable Device : The device to prevent reverse engineering , 2014, IACR Cryptol. ePrint Arch..
[5] Leslie G. Valiant,et al. A general lower bound on the number of examples needed for learning , 1988, COLT '88.
[6] Siddharth Garg,et al. Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes , 2015, NDSS.
[7] David D. Lewis,et al. Heterogeneous Uncertainty Sampling for Supervised Learning , 1994, ICML.
[8] Jeyavijayan Rajendran,et al. CamoPerturb: Secure IC camouflaging for minterm protection , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[9] Burr Settles,et al. Active Learning Literature Survey , 2009 .
[10] Jeyavijayan Rajendran,et al. Security analysis of integrated circuit camouflaging , 2013, CCS.
[11] M. Tehranipoor,et al. Hardware Trojans: Lessons Learned after One Decade of Research , 2016, TODE.
[12] H.-S. Philip Wong,et al. TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Yier Jin,et al. Hardware Security Challenges Beyond CMOS: Attacks and Remedies , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
[14] Sayak Ray,et al. Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).
[15] Meng Li,et al. Provably Secure Camouflaging Strategy for IC Protection , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Jeyavijayan Rajendran,et al. Fault Analysis-Based Logic Encryption , 2015, IEEE Transactions on Computers.
[17] Niklas Een,et al. MiniSat v1.13 - A SAT Solver with Conflict-Clause Minimization , 2005 .
[18] Alex Baumgarten. Preventing integrated circuit piracy using reconfigurable logic barriers , 2009 .
[19] Jeyavijayan Rajendran,et al. Security analysis of logic obfuscation , 2012, DAC Design Automation Conference 2012.
[20] Robert K. Brayton,et al. ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.
[21] Ozgur Sinanoglu,et al. SARLock: SAT attack resistant logic locking , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).
[22] Ankur Srivastava,et al. Mitigating SAT Attack on Logic Locking , 2016, CHES.
[23] Ronald P. Cocchi,et al. Circuit camouflage integration for hardware IP protection , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).