Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces

Verification of cyber-physical systems SW often requires simulation of accurate heterogeneous HW models. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. Furthermore, usually HW computing platforms are “approximated” by using abstracted models that do not accurately reproduce the cycle-based execution of HW components. In this chapter we present the automatic generation of cycle-accurate Simulink blocks from the most popular HW description languages: VHDL and Verilog.

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