Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns
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[1] Masud H. Chowdhury,et al. Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[2] Jacob K. White,et al. FastCap: A Multipole Accelerated 3-D Extraction Program , 1991 .
[3] Yehea I. Ismail,et al. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[4] K. Banerjee,et al. A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation , 2004, IEEE Transactions on Electron Devices.
[5] Wei Zhao. Predictive technology modeling for scaled CMOS , 2009 .
[6] Hiroto Yasuura,et al. A bus delay reduction technique considering crosstalk , 2000, DATE '00.
[7] Yao-Wen Chang,et al. RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Hui-Fen Huang,et al. Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005, IEEE Transactions on Electron Devices.