A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques

This paper presents a high-performance digitizer based on column-parallel single-slope analog-to-digital converter (SS-ADC) topology for readout of a back-illuminated 3-D-stacked CMOS image sensor. To address the high power consumption issue in high speed digital counters, a passing window (PW)-based hybrid counter topology is proposed. In this approach, the memory cells in the digital counters of SS-ADCs are disconnected from the global bus during non-relevant timing. To address the high column fixed pattern noise (FPN) under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. In this technique, the AZ process is employed twice at reset and signal level, respectively. The double AZ scheme not only allows the comparator to serve as a crossing detector around the common-mode level, but it also enables low-voltage comparator design. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column FPN of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling. A single-column digitizer consumes a total power of 66.8 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> and occupies an area of 5.4 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m} \times $ </tex-math></inline-formula> 610 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>.

[1]  Suzuki Atsushi,et al.  A 1/1.7-inch 20Mpixel Back-illuminated Stacked CMOS Image Sensor for New Imaging Applications , 2015 .

[2]  Hiroshi Takahashi,et al.  A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  Masanori Furuta,et al.  6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Fukashi Morishita,et al.  A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit , 2015, IEEE Journal of Solid-State Circuits.

[5]  Charles G. Sodini,et al.  Zero-Crossing-Based Ultra-Low-Power Converters A/D converters that can immediately detect when the input voltage is zero, promise greatly reduced power consumption and elimination of gain and stability concerns. , 2010 .

[6]  Fu-Lung Hsueh,et al.  A 0.66e−rms temporal-readout-noise 3D-stacked CMOS image sensor with conditional correlated multiple sampling (CCMS) technique , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[7]  Abbas El Gamal,et al.  A 256×256 CMOS image sensor with ΔΣ-based single-shot compressed sensing , 2012, 2012 IEEE International Solid-State Circuits Conference.

[8]  Hae-Seung Lee,et al.  A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC , 2012, IEEE Journal of Solid-State Circuits.

[9]  Yoshiaki Takemoto,et al.  A rolling-shutter distortion-free 3D stacked image sensor with −160dB parasitic light sensitivity in-pixel storage node , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[10]  Chih-Cheng Hsieh,et al.  A 3 Megapixel 100 Fps 2.8 $\mu$m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers , 2013, IEEE Journal of Solid-State Circuits.

[11]  Zheng Liu,et al.  A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[12]  Jun Deguchi,et al.  A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[13]  Kawahito Shoji,et al.  A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters , 2016 .

[14]  Minho Kwon,et al.  A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[15]  Kyungmin Kim,et al.  A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[16]  Atsushi Suzuki,et al.  6.1 A 1/1.7-inch 20Mpixel Back-illuminated stacked CMOS image sensor for new imaging applications , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[17]  Yoshiaki Takemoto,et al.  A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode and 2Mpixel 10000fps mode using 4 million interconnections , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[18]  S. Watanabe,et al.  A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change , 2006, IEEE Journal of Solid-State Circuits.

[19]  Tetsuya Hayashida,et al.  6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[20]  Fukushima Noriyuki,et al.  A 17.7Mpixel 120fps CMOS Image Sensor with 34.8Gb/s Readout , 2011 .

[21]  Tadahiro Kuroda,et al.  Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[22]  Fu-Lung Hsueh,et al.  A peripheral switchable 3D stacked CMOS image sensor , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[23]  Douglas Young,et al.  A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[24]  Shoji Kawahito,et al.  A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs , 2012, 2012 IEEE International Solid-State Circuits Conference.

[25]  Yue Chen,et al.  A 0.7e−rms-temporal-readout-noise CMOS image sensor for low-light-level imaging , 2012, 2012 IEEE International Solid-State Circuits Conference.

[26]  I. Takayanagi,et al.  A very low column FPN and row temporal noise 8.9 M-pixel, 60 fps CMOS image sensor with 14bit column parallel SA- ADC , 2008, 2008 IEEE Symposium on VLSI Circuits.

[27]  Shoji Kawahito,et al.  6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[28]  A. Suzuki,et al.  High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[29]  Hae-Seung Lee,et al.  Zero-Crossing-Based Ultra-Low-Power A/D Converters , 2010, Proceedings of the IEEE.

[30]  Hiroshige Goto,et al.  7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[31]  白石 圭,et al.  A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple Sampling PGA (情報センシング) , 2016 .

[32]  Fu-Lung Hsueh,et al.  6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[33]  Daeyun Kim,et al.  Design of a 10-bit CMOS image sensor based on an 8-bit configurable hold-and-go counter , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).