Gate-Pitch Optimization for Circuit Design Using Strain-Engineered Multifinger Gate Structures

Optimal transistor sizing and layout using multifinger gate structures (MFGSs) in mechanical stress-engineered CMOS technology is a major issue. We observe that the pull-down and pull-up delay of an inverter using seven-fingered devices with fan-out-of-four (FO4) load increases by ~ 9% and ~ 14%, respectively, compared with the FO4 delay of a reference inverter using single-finger gate structure. On the other hand, doubling gate-pitch in the above inverter improves the pull-down and pull-up delay by ~ 18% and ~ 23%, respectively, compared with the delay of the reference inverter. In this brief, we present a methodology of transistor sizing and layout optimization for MFGSs in stress-engineered CMOS circuits. For this, we derive and validate a modified model of logical effort (LE), where LE is expressed as a function of the number of fingers (NF) and gate-pitch (Lpp). Using our model, we reduce the error in the estimated delay of a four-stage buffer with FO4 from ~ 9% to ~ 1%. Using our methodology, we improve the circuit performance by 7%.

[1]  Bulusu Anand,et al.  Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[2]  R. Chau,et al.  A 90-nm logic technology featuring strained-silicon , 2004, IEEE Transactions on Electron Devices.

[3]  Ming Cai,et al.  Advanced strain engineering for state-of-the-art nanoscale CMOS technology , 2011, Science China Information Sciences.

[4]  P. Oldiges,et al.  Challenges and Opportunities for High Performance 32 nm CMOS Technology , 2006, 2006 International Electron Devices Meeting.

[5]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[6]  Jong-Ho Lee,et al.  A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs , 2009 .

[7]  Min Chen,et al.  Modeling of layout-dependent stress effect in CMOS design , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[8]  M. Iwai,et al.  Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique , 2009, IEEE Transactions on Electron Devices.

[9]  G. Eneman,et al.  Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study , 2007, IEEE Transactions on Electron Devices.

[10]  E.J. Nowak,et al.  The effective drive current in CMOS inverters , 2002, Digest. International Electron Devices Meeting,.

[11]  P. Bai,et al.  A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[12]  Richard C. Jaeger,et al.  Piezoresistive characteristics of short-channel MOSFETs on (100) silicon , 2001 .

[13]  David Z. Pan,et al.  On stress aware active area sizing, gate sizing, and repeater insertion , 2009, ISPD '09.

[14]  D. Tekleab,et al.  Multi-Layer Model for Stressor Film Deposition , 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.