A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation

Visual feature detection has been widely used in many computer vision applications. In comparison with popular feature detection algorithms, AFFINE-SIFT (ASIFT) achieves the strongest robustness on image illumination, image rotation and image scale transformation, etc., however, since feature vectors of different feature points need to be computed, feature generation of ASIFT exhibits high computing complexity. Meanwhile, it also shows low efficiency on parallel memory accessing since multiple computing processes of feature points need to access the same memory concurrently, which causes memory accessing conflicts and incurs high power consumption. In this work, we improve the feature generation based on a rotation invariant block binary pattern(RIBBP) to reduce computation and design a parallel processing architecture. Meanwhile, a spatial relevance based memory accessing(SRBMA) optimization is performed to improve data reuse and enhance parallel memory accessing. Evaluations using TSMC 65 nm 1P9M LP process show that this work improves the processing speed and energy efficiency of feature generation by 17% and 37.9%, respectively, when compared with state-of-the art work.