Performance-driven placement of multi-million-gate circuits

We survey recent development in placement technology for VLSI layout. In the very deep submicron era, we have to deal with two issues: huge design complexity and wiring-delay dominance of circuit performance. Ever increasing functionality demand and exponentially growing technology capacity together make layout of multi-million-gate circuits everyday work. Because of high-performance requirement and time-to-market pressure, we need effective layout methodologies and tools to help timing-closure. The most natural approach to deal with high complexity is hierarchical placement based on the "divide-and-conquer" paradigm. We will describe how to take advantage of the circuit hierarchy information either passed down from the high-level description or extracted from the netlist structure. Placement will largely determine the circuit performance because it determines the wiring delay, which dominates the gate delay portion in the overall path delay. It must satisfy timing constraints on large number of paths imposed by the front-end synthesis tool; otherwise, we will run into the timing-closure problem. We will present techniques for conveying the path timing constraints to the placement process as well as ECO operations such as resynthesis, logic restructuring/replication, and retiming. This tutorial will conclude with a list of possible directions for future research.