PolyCleaner: Clean your Polynomials before Backward Rewriting to verify Million-gate Multipliers

Nowadays, a variety of multipliers are used in different computationally intensive industrial applications. Most of these multipliers are highly parallelized and structurally complex. Therefore, the existing formal verification techniques fail to verify them. In recent years, formal multiplier verification based on Symbolic Computer Algebra (SCA) has shown superior results in comparison to all other existing proof techniques. However, for non-trivial architectures still a monomial explosion can be observed. A common understanding is that this is caused by redundant monomials also known as vanishing monomials. While several approaches have been proposed to overcome the explosion, the problem itself is still not fully understood. In this paper we present a new theory for the origin of vanishing monomials and how they can be handled to prevent the explosion during backward rewriting. We implement our new approach as the SCA-verifier PolyCleaner. The experimental results show the efficiency of our proposed method in verification of non-trivial million-gate multipliers.

[1]  Rolf Drechsler,et al.  Formal verification of integer multipliers by combining Gröbner basis with logic reduction , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Armin Biere,et al.  Improving and extending the algebraic approach for verifying gate-level multipliers , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  David A. Cox,et al.  Ideals, Varieties, and Algorithms , 1997 .

[4]  Markus Wedler,et al.  Modeling of custom-designed arithmetic components for ABL normalization , 2008, 2008 Forum on Specification, Verification and Design Languages.

[5]  André Rossi,et al.  Formal Verification of Arithmetic Circuits by Function Extraction , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Jacob A. Abraham,et al.  Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems , 2007, IEEE Transactions on Computers.

[7]  Rolf Drechsler,et al.  Equivalence checking using Gröbner bases , 2016, 2016 Formal Methods in Computer-Aided Design (FMCAD).

[8]  David A. Cox,et al.  Ideals, Varieties, and Algorithms: An Introduction to Computational Algebraic Geometry and Commutative Algebra, 3/e (Undergraduate Texts in Mathematics) , 2007 .

[9]  Priyank Kalla,et al.  Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Alan Mishchenko,et al.  Fast Algebraic Rewriting Based on And-Inverter Graphs , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Armin Biere,et al.  Column-wise verification of multipliers using computer algebra , 2017, 2017 Formal Methods in Computer Aided Design (FMCAD).

[12]  Rolf Drechsler,et al.  Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers , 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[13]  Farimah Farahmandi,et al.  Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction , 2015, Microprocess. Microsystems.

[14]  André Rossi,et al.  Verification of gate-level arithmetic circuits by function extraction , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Dominik Stoffel,et al.  Equivalence checking of arithmetic circuits on the arithmetic bit level , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Deepak Kapur,et al.  Mechanical Verification of Adder Circuits using Rewrite Rule Laboratory , 1998, Formal Methods Syst. Des..