Digital pll clock with automatic alignment

An embodiment of the present invention relates to a digital phase-locked loop (ADPLL), which is configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL includes a digitally controlled oscillator configured to generate a variable clock signal which is separated into two signal paths that operate according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to divide the variable clock signal synchronized to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock host monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line output clock signals automatically aligns in time with the variable clock signal.