FRAIGs: A Unifying Representation for Logic Synthesis and Verification

AND-INV graphs (AIGs) are Boolean networks composed of twoinput AND-gates and inverters. In the known applications, such as equivalence checking and technology mapping, AIGs are used to represent and manipulate Boolean functions. AIGs powered by simulation and Boolean satisfiability lead to functionally reduced AIGs (FRAIGs), which are “semi-canonical” in the sense that each FRAIG node has unique functionality among all the nodes currently present in the FRAIG. The paper shows that FRAIGs can be used to unify and enhance many phases of logic synthesis: from the representation of the original and the intermediate netlists derived by logic optimization, through technology mapping over multiple logic structures, to combinational equivalence checking. Experimental results on large public benchmarks confirm the practicality of using FRAIGs throughout the logic synthesis flow.

[1]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[2]  K. Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[4]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[6]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[7]  Logic decomposition during technology mapping , 1995, ICCAD.

[8]  Rolf Drechsler,et al.  Fast and Efficient Equivalence Checking based on NAND-BDDs , 2001 .

[9]  Robert K. Brayton,et al.  Using SAT for combinational equivalence checking , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[10]  Jordi Cortadella.  Bi-Decomposition and Tree-Height Reduction for Timing Optimization , 2002, IWLS.

[11]  Malay K. Ganai,et al.  Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[13]  Kwang-Ting Cheng,et al.  A signal correlation guided ATPG solver and its applications for solving difficult industrial cases , 2003, DAC '03.

[14]  Kwang-Ting Cheng,et al.  A circuit SAT solver with signal correlation guided learning , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[15]  Kenneth L. McMillan,et al.  Interpolation and SAT-Based Model Checking , 2003, CAV.

[16]  A. Kuehlmann.  Dynamic transition relation simplification for bounded property checking , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..