Flash memories: Successes and challenges

Flash memory grew from a simple concept in the early 1980s to a technology that generated close to $23 billion in worldwide revenue in 2007, and this represents one of the many success stories in the semiconductor industry. This success was made possible by the continuous innovation of the industry along many different fronts. In this paper, the history, the basic science, and the successes of fash memories are briefly presented. Flash memories have followed the Moore's Law scaling trend for which finer line widths, achieved by improved lithographic resolution, enable more memory bits to be produced for the same silicon area, reducing cost per bit. When looking toward the future, significant challenges exist to the continued scaling of flash memories. In this paper, I discuss possible areas that need development in order to overcome some of the size-scaling challenges. Innovations are expected to continue in the industry, and flash memories will continue to follow the historical trend in cost reduction of semiconductor memories through the rest of this decade.

[1]  S. Lai,et al.  Flash Memory Technology : Scaling and Integration Challenges , 2002 .

[2]  James D. Plummer,et al.  Performance of the 3-D sidewall flash EPROM cell , 1993, Proceedings of IEEE International Electron Devices Meeting.

[3]  M. Wei,et al.  A Scalable Self-Aligned Contact NOR Flash Technology , 2007, 2007 IEEE Symposium on VLSI Technology.

[4]  Tetsuo Endoh,et al.  A reliable bi-polarity write/erase technology in flash EEPROMs , 1990, International Technical Digest on Electron Devices.

[5]  Greg Atwood,et al.  Intel StrataFlashTM Memory Technology Overview , 1997 .

[6]  Kinam Kim,et al.  Technology for sub-50nm DRAM and NAND flash manufacturing , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[7]  V. N. Kunett,et al.  An In-system Reprogrammable 256k Cmos Flash Memory , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[8]  Konstantin K. Likharev,et al.  Layered tunnel barriers for nonvolatile memory devices , 1998 .

[9]  Tae-Sung Jung,et al.  A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[10]  M. Rosmeulen,et al.  VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices , 2003, IEEE Electron Device Letters.

[11]  Al Fazio,et al.  Intel StrataFlashTM Memory Technology Development and Implementation , 1997 .

[12]  Jangho Park,et al.  Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[13]  J. De Blauwe,et al.  Nanocrystal nonvolatile memory devices , 2002 .

[14]  K. Prall.  Scaling Non-Volatile Memory Below 30nm , 2007, 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop.

[15]  T. Ma,et al.  High-quality MNS capacitors prepared by jet vapor deposition at room temperature , 1992, IEEE Electron Device Letters.

[16]  Mark E. Bauer,et al.  A Multilevel-Cell 32Mb Flash Memory Originally published in ISSCC Digest of Technical Papers 1995 , 2000 .

[17]  Greg Atwood,et al.  A multilevel-cell 32 Mb flash memory , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[18]  G. Atwood,et al.  Future directions and challenges for ETox flash memory scaling , 2004, IEEE Transactions on Device and Materials Reliability.

[19]  S. Mukherjee,et al.  A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM , 1985, 1985 International Electron Devices Meeting.

[20]  Ranjeet Alexis,et al.  A multilevel-cell 32 Mb flash memory , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[21]  Dongchan Kim,et al.  A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[22]  S. Tanaka,et al.  A new flash E2PROM cell using triple polysilicon technology , 1984, 1984 International Electron Devices Meeting.

[23]  T.T.L. Chang,et al.  Oxidized-nitridized oxide (ONO) for high performance EEPROMs , 1982, 1982 International Electron Devices Meeting.

[24]  M. Momodomi,et al.  New ultra high density EPROM and flash EEPROM with NAND structure cell , 1987, 1987 International Electron Devices Meeting.

[25]  M. Lenzlinger,et al.  Fowler-Nordheim tunneling into thermally grown SiO 2 , 1968 .

[26]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .