Design of leaky bucket access control schemes in ATM networks

Depending on what enforcement action is taken and whether or not there is a 'shaping' buffer, four versions of the leaky bucket scheme are considered, and their cell loss performance is compared in conjunction with a statistical multiplexer. Based on the best-performing version, three architectures are proposed. Among them, a novel algorithm and its implementation method are proposed to accommodate a large number of virtual channel connections on each incoming STS-3c channel. A VLSI chip (called a sequencer), containing about 200 K CMOS transistors, has been designed to implement the architecture.<<ETX>>

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