Improved decoding algorithm for high reliable reed muller coding

A new decoding technique for triple error Reed-Muller codes is proposed. In the best of our knowledge this is the first time that Reed-Muller Codes (RMC) as on-chip triple error correcting scheme is reported. We’ve compared the area, delay and power overhead for incorporating RMC and widely used Hamming Codes into a register file. The RMC on-chip results in 4.4X MTTF improvement with fault rate λ=10−4 and 5X reliability improvement in 512MB memory with λ=10−5 upsets/bit per day sacrificing area power and delay.

[1]  K. Itoh.  Trends in megabit DRAM circuit design , 1989, International Symposium on VLSI Technology, Systems and Applications,.

[2]  K. Soumyanath,et al.  Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[3]  Cecilia Metra,et al.  Error Correcting Strategy for High Speed and High Density Reliable Flash Memories , 2003, J. Electron. Test..

[4]  Dhiraj K. Pradhan,et al.  LPRAM: a novel low-power high-performance RAM design with testability and scalability , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Luca Benini,et al.  Error control schemes for on-chip communication links: the energy-reliability tradeoff , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Y. Nakagome,et al.  Trends in low-power RAM circuit technologies , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[7]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[8]  Dhiraj K. Pradhan,et al.  Multiple Upsets Tolerance in SRAM Memory , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[9]  Vivek De,et al.  Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process , 2004 .

[10]  Jennifer D. Key,et al.  Designs and their codes , 1992, Cambridge tracts in mathematics.

[11]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[12]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[13]  Irving S. Reed,et al.  A class of multiple-error-correcting codes and the decoding scheme , 1954, Trans. IRE Prof. Group Inf. Theory.

[14]  Janak H. Patel,et al.  Reliability of scrubbing recovery-techniques for memory systems , 1990 .

[15]  M. Margala,et al.  Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation-a comparative study , 1998, IEEE J. Solid State Circuits.

[16]  Dhiraj K. Pradhan,et al.  Error-Control Techniques for Logic Processors , 1972, IEEE Transactions on Computers.

[17]  Masao Kasahara,et al.  New decoding algorithm for Reed-Muller codes , 1982, IEEE Trans. Inf. Theory.

[18]  Kiyoo Itoh,et al.  Power Reduction Techniques in Megabit DRAM's , 1986 .

[19]  Dhiraj K. Pradhan,et al.  Highly Reliable Power Aware Memory Design , 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

[20]  Steven Roman,et al.  Coding and information theory , 1992 .

[21]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.