Generation of Dislocations and Stacking Faults at Surface Heterogeneities in Silicon

Dislocation and stacking fault generation around submicron‐sized surface pits in shallow diffused bipolar transistors is examined. Under the combined action of the stress concentration effect of surface pits and phosphorus diffusion induced stresses, crystallographic defects are generated in the emitter area of shallow diffused transistors. Stacking faults are identified as sessile faults surrounding the micropits. Mechanisms of dislocation generation are examined and their applicability to the present results discussed. It is shown that the presence of nonplanar surfaces at discrete regions can introduce an additional diffusion front into the crystal and produce an increase in stress as well as an increase in the solute concentration leading to localized plastic flow. High‐concentration phosphorus diffusions introduce extensive dislocation networks throughout the emitter area and cause stacking fault annihilation.

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