Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide Devices

A new 2×V<sub>DD</sub>-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only 1 xV<sub>DD</sub> devices can successfully transmit and receive 2×V<sub>DD</sub> signal. Utilizing this technique with only 1 xV<sub>DD</sub> devices, the digital logic gates are also modified to have 2 xV<sub>DD</sub>-tolerant capability. With 2 V<sub>DD</sub>-tolerant logic gates, the PVT variation detector has been implemented to detect PVT variations from 2×V<sub>DD</sub> signal and provide compensation control to the 2×V<sub>DD</sub>-tolerant I/O buffer without suffering the gate-oxide overstress issue.

[1]  H. Fujisawa,et al.  A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[2]  S. Mittl,et al.  Accelerated gate-oxide breakdown in mixed-voltage I/O circuits , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

[3]  Ping-Ying Wang,et al.  A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes , 2009, IEEE Journal of Solid-State Circuits.

[4]  E. C. Dijkmans,et al.  A 3/5 V compatible I/O buffer , 1995 .

[5]  Chua-Chin Wang,et al.  0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Chris H. Kim,et al.  A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias , 2009, 2009 Symposium on VLSI Circuits.

[7]  Soon-Kyun Shin,et al.  A slew rate controlled output driver using PLL as compensation circuit , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[8]  Chen Ih-Chin,et al.  The effect of channel hot-carrier stressing on gate-oxide integrity in MOSFETs , 1988 .

[9]  J. L. Prince,et al.  Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise , 1993 .

[10]  J. Xu,et al.  Die-package stress interaction impact on transistor performance , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[11]  Chulwoo Kim,et al.  A $\hbox{Gb/s}+$ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  G. P. Singh,et al.  High-voltage-tolerant I/O buffers with low-voltage CMOS process , 1999, IEEE J. Solid State Circuits.

[13]  Abdelhalim Bendali,et al.  A 1-V CMOS Current Reference With Temperature and Process Compensation , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Y.T. Tee,et al.  Design techniques to combat process, temperature and supply variations in Bluetooth RFIC , 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.

[15]  Ming-Dou Ker,et al.  Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique , 2006, IEEE Journal of Solid-State Circuits.

[16]  T. W. Hughes,et al.  Properties of high-voltage stress generated traps in thin silicon oxide , 1996 .

[17]  Wang Yu,et al.  Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Takayasu Sakurai,et al.  3.3V-5V compatible I/O circuit without thick gate oxide , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[19]  R. Degraeve,et al.  Consistent model for short-channel nMOSFET after hard gate oxide breakdown , 2002 .

[20]  Chulwoo Kim,et al.  A One-Cycle Lock Time Slew-Rate-Controlled Output Driver , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[21]  Zhongyuan Chang,et al.  A self-biased PLL with current-mode filter for clock generation , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[22]  J. L. Prince,et al.  Simultaneous switching ground noise calculation for packaged CMOS devices , 1991 .

[23]  M. Bazes.  Output buffer impedance control and noise reduction using a speed-locked loop , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).