A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm2.

[1]  Behzad Razavi,et al.  Design considerations for direct-conversion receivers , 1997 .

[2]  R. Weigel,et al.  Digital Adaptive IIP2 Calibration Scheme for CMOS Downconversion Mixers , 2008, IEEE Journal of Solid-State Circuits.

[3]  Asad A. Abidi Direct-conversion radio transceivers for digital communications , 1995 .

[4]  Pui-In Mak,et al.  On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Zhih-Siou Cheng,et al.  A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications , 2006, 2006 International Symposium on VLSI Design, Automation and Test.

[6]  Calvin Plett,et al.  A 5 GHz direct-conversion receiver with DC offset correction , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).