A phase detector for 12.5Gbps clock and data recovery with optimal detection

We propose a phase detector using a matched filter that maximizes the performance for a given input noise condition. The matched filter performs optimal detection that maximizes the signal-to-noise ratio (SNR) at the sampling instant. The phase detector is designed for a 12.5Gbps clock-and-data recovery (CDR) circuit. Through optimal detection, the system rejects various types of noise, such as narrowband colored noise or additive white noise. The performance of the proposed phase detector is compared with a typical one through simulation. A delay-locked loop (DLL)-based clock recovery circuit is also implemented with the proposed phase detector and shows stable lock-in operation with the data SNR as low as 4.69dB. It also shows 2.2ps of root mean square (RMS) clock jitter when the second harmonic clock signal leakage degrades the data SNR to 5dB.

[1]  Marvin K. Simon.  Nonlinear Analysis of an Absolute Value Type of an Early-Late Gate Bit Synchronizer , 1970 .

[2]  Manoj Sachdev,et al.  Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[3]  B. Razavi,et al.  A CMOS interface circuit for detection of 1.2 Gb/s RZ data , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[4]  Mark Horowitz,et al.  A 700-Mb/s/pin CMOS signaling interface using current integrating receivers , 1997 .

[5]  P. Zicari,et al.  A high flexible Early-Late Gate bit synchronizer in FPGA-based software defined radios , 2008, 2008 4th European Conference on Circuits and Systems for Communications.