Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Abstract A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 × 10 18 and 1 × 10 19  cm −3 . The developed model is suitable for describing the current–voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters.

[1]  O. Faynot,et al.  Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm , 2012, IEEE Electron Device Letters.

[2]  Marcelo Antonio Pavanello,et al.  Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors , 2013 .

[3]  B. McCarthy,et al.  SOI gated resistor: CMOS without junctions , 2009, 2009 IEEE International SOI Conference.

[4]  A. Kranti,et al.  A Simulation Comparison between Junctionless and Inversion-Mode MuGFETs , 2011 .

[5]  Jean-Michel Sallese,et al.  Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime , 2013 .

[6]  G. Ghibaudo,et al.  Separation of surface accumulation and bulk neutral channel in junctionless transistors , 2014 .

[7]  Marcelo Antonio Pavanello,et al.  Compact core model for Symmetric Double-Gate Junctionless Transistors , 2014 .

[8]  Jean-Pierre Colinge,et al.  FinFETs and Other Multi-Gate Transistors , 2007 .

[9]  Bruna Cardoso Paz,et al.  Compact model for short-channel symmetric double-gate junctionless transistors , 2015 .

[11]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[13]  K. K. Young Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[14]  Chi-Woo Lee,et al.  Nanowire transistors without junctions. , 2010, Nature nanotechnology.

[15]  Sylvain Barraud,et al.  Revisited parameter extraction methodology for electrical characterization of junctionless transistors , 2013 .

[16]  B. Iñíguez,et al.  Compact model for short channel symmetric doped double-gate MOSFETs , 2008 .

[17]  Bruna Cardoso Paz,et al.  Double-gate junctionless transistor model including short-channel effects , 2015 .

[18]  Hyuck-In Kwon,et al.  A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure , 2013 .

[19]  Michael Graef,et al.  Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects , 2014, Microelectron. J..

[20]  R. E. Thomas,et al.  Carrier mobilities in silicon empirically related to doping and field , 1967 .

[21]  M. Estrada,et al.  Proposal of compact analytical modeling for trigate junctionless nanowire transistors , 2015, 2015 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC).

[22]  G. Pei,et al.  FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .

[23]  Alexander Kloes,et al.  3-D compact model for nanoscale junctionless triple-gate nanowire MOSFETs, including simple treatment of quantization effects , 2015 .

[24]  Michael Graef,et al.  Compact Model for Short-Channel Junctionless Accumulation Mode Double Gate MOSFETs , 2014, IEEE Transactions on Electron Devices.

[25]  G. Ghibaudo,et al.  Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs , 2012, IEEE Transactions on Electron Devices.