Relaxation effect on cycling on NOR flash memories

This study is driven by the need to improve endurance of Flash memory. First of all, relaxation during cycling is performed at high temperature. An effect of relaxation has been noticed on erased threshold voltage at high temperature whereas at room temperature, no effect of relaxation is observed. Relaxation implies a recovery of interface state. Then, an experiment of retention after cycling is achieved. At equivalent relaxation time, trap density remains lower for experiment with delay during cycling than for delay after cycling.

[1]  J. Lien,et al.  Degradations due to hole trapping in flash memory cells , 1989, IEEE Electron Device Letters.

[2]  John S. Suehle,et al.  Electric field dependent dielectric breakdown of intrinsic SiO/sub 2/ films under dynamic stress , 1996, Proceedings of International Reliability Physics Symposium.

[3]  P. Kalavade,et al.  Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling , 2004, IEEE Transactions on Device and Materials Reliability.

[4]  K. Suh,et al.  The Effect of Trapped Charge Distributions on Data Retention Characteristics of nand Flash Memory Cells , 2007, IEEE Electron Device Letters.

[5]  Romain Laffont,et al.  Effect of AC stress on oxide TDDB and trapped charge in interface states , 2014, 2014 International Symposium on Integrated Circuits (ISIC).

[6]  Kuniyoshi Yoshikawa,et al.  Degradation mechanism of flash EEPROM programming after program/erase cycles , 1993, Proceedings of IEEE International Electron Devices Meeting.

[7]  Kinam Kim,et al.  Temperature Dependence of Endurance Characteristics in NOR Flash Memory Cells , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[8]  A. Visconti,et al.  Reliability Characterization Issues for Nanoscale Flash Memories: A Case Study on 45-nm NOR Devices , 2013, IEEE Transactions on Device and Materials Reliability.