Design Trade off and Performance Analysis of Router Architectures in Network-on-Chip

Abstract On chip interconnection networks simplify the challenges of integrating large number of processing elements. Routers are backbone of networks. Buffers and crossbar in router consumes significant area and power of network. Reducing buffers could lead to degradation of network performance. Dual Xbar router architecture combines buffered and bufferless feature to reduce buffer read/write energy with dual crossbars. While Switch folding technique introduced to reduce wire density and decrease muxes in crossbar by increasing resource utilization. In this paper, we propose Folded Dual Xbar architecture by combining the Dual Xbar and Folding technique in order to get advantages of both architectures. Performance of architectures is evaluated using OMNET++ platform under different load conditions. Simulation results shows that there is slight increase in throughput and reduction in buffer read/write energy by average 46% at high loads in proposed 2-Folded Dual Xbar as compared to conventional architecture. Proposed 3-Folded Dual Xbar results at least 16.6% increase in throughput as compared to conventional architecture with 43-45% reduced buffer read/write energy but slight increase in crossbar. Throughput of 3-Folded Dual Xbar decreased only by 5-7% as compared to Dual Xbar with distributed wire density advantage.

[1]  Janet Roveda,et al.  Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures , 2009, 2009 Asia and South Pacific Design Automation Conference.

[2]  Natalie D. Enright Jerger,et al.  SCARAB: A single cycle adaptive routing and bufferless network , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[3]  Benoît Dupont de Dinechin,et al.  K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph , 2012, 2012 International Conference on Embedded Computer Systems (SAMOS).

[4]  Muhammad E. S. Elrabaa,et al.  Improved Modified Fat-Tree Topology Network-on-Chip , 2011, J. Circuits Syst. Comput..

[5]  Kun-Lin Tsai,et al.  A priority based output arbiter for NoC router , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[6]  K. Orthner.  Applying the Benefits of Network on a Chip Architecture to FPGA System Design Intel ® FPGA , 2010 .

[7]  Chifeng Wang,et al.  Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip , 2014, Microprocess. Microsystems.

[8]  Bill Lin,et al.  Design of a High-Throughput Distributed Shared-Buffer NoC Router , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

[9]  Atsushi Matsumoto,et al.  High-Throughput Compact Delay-Insensitive Asynchronous NoC Router , 2014, IEEE Transactions on Computers.

[10]  M. Karthikeyan,et al.  Comparative performance evaluation of power and area Network on Chip (NoC) architectures , 2012, 2012 IEEE International Conference on Computational Intelligence and Computing Research.

[11]  Israel Cidon,et al.  HNOCS: Modular open-source simulator for Heterogeneous NoCs , 2012, 2012 International Conference on Embedded Computer Systems (SAMOS).

[12]  Avinash Karanth Kodi,et al.  Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture , 2011, Microprocess. Microsystems.

[13]  John Kim,et al.  Low-cost router microarchitecture for on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[14]  Bevan M. Baas,et al.  RoShaQ: High-performance on-chip router with shared queues , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[15]  Bill Lin,et al.  A High-Throughput Distributed Shared-Buffer NoC Router , 2009, IEEE Computer Architecture Letters.

[16]  Emmanouil Kalligeros,et al.  Switch folding: Network-on-Chip routers with time-multiplexed output ports , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).