Testing FPGA delay faults in the system environment is very different from "ordinary" delay fault testing
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[1] Sungho Kang,et al. Fastpath: a path-delay test generator for standard scan designs , 1994, Proceedings., International Test Conference.
[2] Andrzej Krasniewski. Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs , 2000, FPL.
[3] Russell Tessier,et al. Interconnect testing in cluster-based FPGA architectures , 2000, Proceedings 37th Design Automation Conference.
[4] Robert K. Brayton,et al. Delay fault coverage, test set size, and performance trade-offs , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Yervant Zorian,et al. Test of RAM-based FPGA: methodology and application to the interconnect , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[6] Michel Renovell,et al. A Specific Test Methodology for Symmetric SRAM-Based FPGAs , 2000, FPL.
[7] Charles E. Stroud,et al. Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[8] Nur A. Touba,et al. Configuration self-test in FPGA-based reconfigurable systems , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[9] Hideo Fujiwara,et al. Universal Fault Diagnosis for Lookup Table FPGAs , 1998, IEEE Des. Test Comput..
[10] Kwang-Ting Cheng,et al. Delay testing for non-robust untestable circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).
[11] Andrzej Krasniewski. Application-dependent testing of FPGA delay faults , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.
[12] Charles E. Stroud,et al. Built-in self-test of FPGA interconnect , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[13] Kwang-Ting Cheng,et al. Primitive delay faults: identification, testing, and design for testability , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] Sudhakar M. Reddy,et al. Fast Identification of Robust Dependent Path Delay Faults , 1995, 32nd Design Automation Conference.
[15] Ping Chen,et al. Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) , 1996, Proceedings of 14th VLSI Test Symposium.
[16] Yervant Zorian,et al. Novel technique for testing FPGAs , 1998, Proceedings Design, Automation and Test in Europe.
[17] Fabrizio Lombardi,et al. Testing configurable LUT-based FPGA's , 1998, IEEE Trans. Very Large Scale Integr. Syst..