Performance and routability improvements for routability-driven FPGA routers

Routing FPGAs (Verma, 1999) is a challenging problem because of the relative scarcity of routing resources represented in wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals (McMurchie, 1995). This paper presents some enhancements to improve both the performance and routability of the routability-driven routing using the versatile place and route VPR routing tool (Betz, 1999). Testing MCNC benchmarks has shown the efficiency of these enhancements

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