SAR ADC architecture with 98% reduction in switching energy over conventional scheme
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[1] Franco Maloberti,et al. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.
[2] Soon-Jyh Chang,et al. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.
[3] S. Godsill,et al. The Institution of Engineering and Technology Seminar on Target Tracking and Data Fusion , 2008 .
[4] Jon Guerber,et al. Merged capacitor switching based SAR ADC with highest switching energy-efficiency , 2010 .
[5] Brian P. Ginsburg,et al. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[6] Yvonne Y. H. Lam,et al. Low-energy and area-efficient tri-level switching scheme for SAR ADC , 2012 .