Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC

In this paper, we propose a low-power all-digital phaselocked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phaseinterpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm 2 using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is –120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

[1]  Matthew Z. Straayer,et al.  A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.

[2]  Stephan Henzler,et al.  A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion , 2008, IEEE Journal of Solid-State Circuits.

[3]  Poras T. Balsara,et al.  Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[4]  Suki Kim,et al.  Wide-Band Fine-Resolution DCO with an Active Inductor and Three-Step Coarse Tuning Loop , 2011 .

[5]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[6]  Matthew Z. Straayer,et al.  A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  O. Moreira-Tamayo,et al.  All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[8]  Pavan Kumar Hanumolu,et al.  A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.

[10]  Pavan Kumar Hanumolu,et al.  A Digital PLL With a Stochastic Time-to-Digital Converter , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  R.B. Staszewski,et al.  TDC-based frequency synthesizer for wireless applications , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

[12]  D. Leenaerts,et al.  A SiGe BiCMOS 1ns fast hopping frequency synthesizer for UWB radio , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..