Hardware-assisted dynamic power and thermal management in multi-core SoCs

The use of efficient and dynamic power dissipation management mechanisms is crucial in upcoming, complex and dynamic multi-core Systems-on-Chip. In such systems, static approaches are inadequate to capture the dynamic system behavior, while at the same time, their complexity makes the use of extensive, accurate simulation-based power estimation computationally difficult or prohibitive. This paper proposes dynamically programmable hardware monitors with insignificant cost in silicon area, easily integrated with multi-core Systems-on-Chip, which act non-intrusively in support of real-time identification of tasks' behavior and adaptive management of varying workload. We extract instruction and data activity metrics in order to estimate applications power phase in less than 10 clock cycles. Using "binary" on/off accelerators in conjuction with a distributed algorithm for workload throttling fast and efficient power throttling is achieved proportional to tasks power profile.