Low voltage low output impedance high bandwidth flipped voltage follower cell

This paper proposes the low-voltage low-output impedance high bandwidth flipped voltage follower cell operating at power supply of +1 V. The negative feedback is applied to reduce the output impedance of cell; the same is also done to enhance the bandwidth. The stability of the proposed circuits has been performed by frequency domain approach using phase margin calculations. The results are simulated in TSMC 0.18 um technology using TSPICE and the small signal analysis has also carried out for validating the results mathematically. To justify the physical verification of the proposed circuit, the layout of the cell is implemented using 1.2 um tanner database file and on the same time is scaled to 0.18 um by applying SCMOS technique. The layout process of the circuit is carried out by keeping in mind the design rules (NO DRC errors) and at the last layout versus schematic (LVS) is also performed to prove that the layout which is being implemented, belongs to the same schematic. All the results shown are plotted to prove the effectiveness of the proposed cell.