An Improved SysML-Based Failure Model for Safety Verification By Simulation

System design errors are more likely to occur in modern systems because of their steadily increasing size and complexity. Failures due to system design errors can cause safety-related accidents in the system, resulting in extensive damage to people and property. Therefore, international standards organizations, such as the U.S. Department of Defense and the International Electrotechnical Commission, have established international safety standards to ensure system safety, and recommend that system design and safety activities should be integrated. Recently, the safety of a system has been verified by modeling through a model-based system design. On the other hand, system design and safety activities have not been integrated because the model for system design and the failure model for safety analysis and verification were developed using different modeling language platforms. Furthermore, studies using UML or SysML-based failure models for deriving safety requirements have shown that these models have limited applicability to safety analysis and verification. To solve this problem, it is essential to extend the existing methods for failure model implementation. First, an improved SysML-based failure model capable of integrating system design and safety verification activities should be produced. Next, this model should help verify whether the safety requirements derived via the failure model are reflected properly in the system design. Therefore, this paper presents the concept and method of developing a SysML-based failure model for an automotive system. In addition, the failure model was simulated to verify the safety of the automotive system. The results show that the improved SysML-based failure model can support the integration of system design and safety verification activities.