Optimizing reliability in a two-level distributed architecture for wafer scale integration

Fault tolerance to support mission life reliability is a key consideration in many system applications. Redundancy for defect tolerance, i.e., yield enhancement, and wafer-level reliability enhancement have been standard practice since the advent of wafer scale technology. The Reliability-Hardware Quotient (RHQ) is an example of a fundamental composite metric which is useful for identifying the optimal design point in a VSLI or wafer scale system. In this paper, the RHQ metric is applied to the problem of optimizing a two-level distributed (parallel) processing architecture. In particular, a graphical optimization technique using the 3D and contour plot features of Mathematica is introduced which characterizes the trade space and identifies the optimum design point. The constraints of wafer scale technology can be superimposed upon the optimal solution space either to identify the limits of a given wafer scale implementation or to show what level of wafer scale technology is needed to achieve the optimum design.<<ETX>>