The DRAM Array

This chapter begins a more detailed examination of standard DRAM array elements. This examination is necessary for a clear understanding of fundamental DRAM elements and how they are used in memory block construction. A common point of reference is required before considering the analysis of competing array architectures. Included in this chapter is a detailed discussion of mbits, array configurations, sense amplifier elements, and row decoder elements.

[1]  T. Yamada,et al.  A 16mb Dram with an Open Bit-Line Architecture , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[2]  K. Itoh Trends in megabit DRAM circuit design , 1989, International Symposium on VLSI Technology, Systems and Applications,.

[3]  Hideto Hidaka,et al.  A 34 ns 256 Mb DRAM with boosted sense-ground scheme , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[4]  Yukihito Oowaki,et al.  Open/folded bit-line arrangement for ultra-high-density DRAM's , 1994 .

[5]  N. Tanabe,et al.  A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[6]  Toshinori Morihara,et al.  Disk-Shaped Stacked Capacitor Cell for 256 Mb Dynamic Random-Access Memory , 1994 .

[7]  Takamaro Kikkawa,et al.  A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs , 1990, International Technical Digest on Electron Devices.

[8]  Hideto Hidaka,et al.  A divided/shared bit-line sensing scheme for ULSI DRAM cores , 1991 .

[9]  R. Kraus,et al.  Analysis and reduction of sense-amplifier offset , 1989 .

[10]  H. H. Chao,et al.  Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs , 1984 .

[11]  John K. DeBrosse,et al.  The evolution of IBM CMOS DRAM technology , 1995, IBM J. Res. Dev..

[12]  Kiyoo Itoh,et al.  A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure , 1988 .

[13]  Takanori Saeki,et al.  A boosted dual world-line decoding scheme for 256 Mb DRAMs , 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

[14]  Gary B. Bronner,et al.  A Fully Planarized 0.25 m CMOS Technology , 1991 .

[15]  H. Hidaka,et al.  A Twisted Bit Line Technique for Multi-Mb Drams , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[16]  K. Hoffmann,et al.  Optimized sensing scheme of DRAMs , 1989 .