Low complexity pipeline FFT processor for MIMO-OFDM systems

In this paper, we propose a low complexity pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving (4 × 4) antennas. The proposed FFT processor is based on multi-channel structure which enables to support multiple data streams efficiently. With mixed-radix algorithm, the number of non-trivial multiplications of the proposed FFT processor are decreased. Implementation results show that the proposed FFT processor reduces the required number of logic gates by 25% over the conventional 4-channel R4MDC FFT processor which has been considered to be the most area-efficient FFT processor for 4 × 4 MIMO-OFDM systems.

[1]  T. Sansaloni,et al.  Efficient pipeline FFT processors for WLAN MIMO-OFDM systems , 2005 .

[2]  E. V. Jones,et al.  A pipelined FFT processor for word-sequential data , 1989, IEEE Trans. Acoust. Speech Signal Process..

[3]  Geoffrey Ye Li,et al.  Broadband MIMO-OFDM wireless communications , 2004, Proceedings of the IEEE.

[4]  Yunho Jung,et al.  New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications , 2003, IEEE Trans. Consumer Electron..

[5]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.

[6]  Shousheng He,et al.  Designing pipeline FFT processor for OFDM (de)modulation , 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

[7]  Helmut Bölcskei,et al.  MIMO-OFDM wireless systems: basics, perspectives, and challenges , 2006, IEEE Wirel. Commun..