A direct digital modulation technique for GSM/PCS/DCS applications using a 24 bit multi-accumulator fractional-n synthesizer

This paper describes the implementation of a 0.5 μm BiCMOS Fractional-N synthesizer which incorporates a GMSK data filter which modulates the Fractional-N divider of the synthesizer. This IC (MC145211) also includes a DAC that provides a dual port modulation output to the VCO. This allows PLL loop bandwidth optimisation independent of the modulation performance. The charge pumps are dual-state to provide linearity and eliminate the wide area dead-zone caused by the 26 MHz reference used in the phase detector. Phase noise of -105 dBc/Hz is achievable within the loop Bandwidth for GSM. GSM Global Phase Error of less than 2° RMS is achievable. (11 pages)