Modellierung rekonfigurierbarer Systemarchitekturen
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[1] Jürgen Teich,et al. System-Level Synthesis Using Evolutionary Algorithms , 1998, Des. Autom. Embed. Syst..
[2] Petru Eles,et al. Hierarchical modeling and verification of embedded systems , 2001, Proceedings Euromicro Symposium on Digital Systems Design.
[3] Petru Eles,et al. An approach to incremental design of distributed embedded systems , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[4] Christian Haubelt,et al. System design for flexibility , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[5] Jürgen Teich,et al. Representation of function variants for embedded system optimization and synthesis , 1999, DAC '99.
[6] Shuvra S. Bhattacharyya,et al. Quasi-static scheduling of reconfigurable dataflow graphs for DSP systems , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).
[7] Uli Kutter,et al. Literatur. , 1941, Subjekt.
[8] Ranga Vemuri,et al. MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs , 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).