论文信息 - All-Digital PLL Using Pulse-Based DCO

All-Digital PLL Using Pulse-Based DCO

A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.1 um CMOS process is presented. The pulse- based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7 ps and 44 ps at 450-MHz, respectively. Power consumption is 16.2 mW at 450-MHz.

Jen-Chieh Liu | Kuo-Hsing Cheng | Hong-Yi Huang

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