Bounding loop iterations for timing analysis
暂无分享,去创建一个
David B. Whalley | Mikael Sjödin | Christopher A. Healy | Viresh Rustagi | D. Whalley | Mikael Sjödin | V. Rustagi
[1] David B. Whalley,et al. Timing analysis for data caches and set-associative caches , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.
[2] A. D. Stoyenko,et al. Real-time Euclid: a language for reliable real-time systems , 1989 .
[3] David B. Whalley,et al. Supporting the specification and analysis of timing constraints , 1996, Proceedings Real-Time Technology and Applications.
[4] Alfred V. Aho,et al. Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.
[5] David A. Patterson,et al. Computer Architecture: A Quantitative Approach , 1969 .
[6] Sharad Malik,et al. Efficient microarchitecture modeling and path analysis for real-time software , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.
[7] F. H. Sumner. Computer Architecture, second edition , 1978 .
[8] Jan Gustafsson,et al. Deriving Annotations for Tight Calculation of Execution Time , 1997, Euro-Par.
[9] David B. Whalley,et al. Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.
[10] Alan C. Shaw,et al. Experiments with a program timing tool based on source-level timing schema , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.
[11] Manuel E. Benitez,et al. A portable global optimizer and linker , 1988, PLDI '88.
[12] David B. Whalley,et al. Integrating the timing analysis of pipelining and instruction caching , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.