The TRIMAGE PET Data Acquisition System: Initial Results

We present the first results obtained with a prototype of the PET read-out electronics of the trimodal PET/MRI/EEG TRIMAGE scanner. The read-out is based on the 64-channel TRIROC ASIC and on an acquisition board that will control up to 12 ASICs. The output of each ASIC is processed in parallel and sent to a host system that in the final version will receive data from 18 acquisition boards. Blocks of 64 SiPMs are one-to-one coupled to a dual-layer staggered LYSO crystal matrix and read by a single ASIC. The FPGA reads the sparse output from the ASICs and reconstructs for each event a full image of the light pattern coming from the LYSO matrix. This pattern can be then processed on-line or sent to the host PC for post-processing. Early tests were conducted by using a prototype board with single LYSO crystals of ${3.3} \textrm {mm}\times {3.3} \textrm {mm} \times {8} \textrm {mm}$ and dual layer staggered LYSO matrices. Results show that the ASIC can sustain input rates above 58 kHz on all its channels, with small variations depending on the discriminating thresholds, being this limit due its digital output stage. With the single crystals setup, we obtained an energy resolution of 10.7% at 511 keV and a coincidence time resolution of 420 ps FWHM. With the staggered matrix the obtained mean energy resolution was 16% on the top layer and 18% on the bottom layer. The flood maps obtained with the LYSO matrix setup show that the pixels on both the staggered levels are clearly identifiable.