Two-dimensional carrier flow in a transistor structure under non-isothermal conditions

Summary form only given, as follows. A two-dimensional mathematical model is developed to predict the internal behavior of power transistors operating under steady-state conditions. This model includes the internal self heating effects in power transistors and is applicable to predict the transistor behavior under high current and high voltage operating conditions. The complete set of partial differential equations governing the bipolar semiconductor device behavior under non-isothermal conditions is solved by numerical techniques without assuming internal junctions and other conventional approximations. No restrictions are made on the choice of the doping profile, mobility dependence, boundary conditions for external contacts, generation-recombination model and the injection level. Computed results of the analysis of a typical power transistor design are presented for various operating conditions. The current density, electrostatic potential, carrier charge density and temperature distribution plots within the transistor structure illustrate the combined effect of the electro-thermal interaction, base conductivity modulation, current crowding, base push-out, space charge layer widening and current spreading phenomena in power transistors.