Iterative Application Mapping with TSV Placement Strategy for Design a 3D NoC-Based Multi-Core Systems

Iterative mapping algorithms start with an initial mapping solution which is improved further by introducing changes into it. The problem can be viewed as the partitioning problem in VLSI physical design process. In a partitioning process, highly connected modules are put into the same partition to reduce the wiring overhead. Similarly, a mapping process has the objective to keep the highly communicating tasks close to each other.

[1]  Frédéric Pétrot,et al.  A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies , 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

[2]  Partha Pratim Pande,et al.  Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.

[3]  Kiyoung Choi,et al.  A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[4]  Sung Kyu Lim,et al.  A study of Through-Silicon-Via impact on the 3D stacked IC layout , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[5]  Santanu Chattopadhyay,et al.  Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

[6]  Radu Marculescu,et al.  On-chip traffic modeling and synthesis for MPEG-2 video applications , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Santanu Chattopadhyay,et al.  Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router , 2012, Microprocess. Microsystems.

[8]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[9]  Salvatore Monteleone,et al.  Cycle-Accurate Network on Chip Simulation with Noxim , 2016, ACM Trans. Model. Comput. Simul..

[10]  Hannu Tenhunen,et al.  Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[11]  K.-C. Chang,et al.  Low-power algorithm for automatic topology generation for application-specific networks on chips , 2008, IET Comput. Digit. Tech..

[12]  Santanu Chattopadhyay,et al.  Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[14]  Santanu Chattopadhyay,et al.  Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip , 2014, J. Syst. Archit..

[15]  Xiaowei Li,et al.  Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[16]  Frédéric Pétrot,et al.  Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs , 2013, IEEE Transactions on Computers.

[17]  Santanu Chattopadhyay,et al.  A survey on application mapping strategies for Network-on-Chip design , 2013, J. Syst. Archit..

[18]  Hannu Tenhunen,et al.  A study of Through Silicon Via impact to 3D Network-on-Chip design , 2010, 2010 International Conference on Electronics and Information Engineering.