Design of An Extended On-chip Real Time Debug System

A design of on-chip debug facilities for a CPU not supporting debug mode is introduced.It preserves structural integrity of the CPU by utilizing some add-on units including CPU monitor,debug control,clock/reset management and a JTAG compatible debug access port to implement all the higher level debug functions with only a small hardware overhead.The debug command configuration and execution are totally independent of the CPU so that the CPU can run in real time.