Reliability degradation of MOS transistors originated from plasma process-induced charging of circuit blocks and detected with fWLR methods

The effect of plasma process induced charging of remote circuit blocks and consequently the reliability damage on a single MOS transistor which is connected to such a circuit block is demonstrated for the first time. Traditional methods of characterizing gate electrode antennas do not cover this topic. A new product relevant plasma-induced damage test structure type is introduced as well as a new definition of the antenna ratio to describe the damage potential of a circuit block. This investigation is carried out for a standard 130nm bulk-Si technology with a deep trench process.

[1]  P. K. Aum,et al.  Controlling plasma charge damage in advanced semiconductor manufacturing. Challenge of small feature size device, large chip size, and large wafer size , 1998 .

[2]  A. Amerasekera,et al.  Antenna device reliability for ULSI processing , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[3]  A. Aal A procedure for reliability control and optimization of mixed-signal smart power CMOS pocesses , 2003, Microelectron. Reliab..

[4]  Kin P. Cheung,et al.  Plasma Charging Damage , 2000 .

[5]  A. Martin,et al.  Fast Wafer Level Reliability Monitoring: Quantification of Plasma-Induced Damage Detected on Productive Hardware , 2009, IEEE Transactions on Device and Materials Reliability.

[6]  David Smeets,et al.  WLR monitoring methodology for assessing charging damage on oxides thicker than 4nm using antenna structures , 2001, 2001 IEEE International Integrated Reliability Workshop. Final Report (Cat. No.01TH8580).

[7]  G. Sery,et al.  A model for n-well junction effect on gate-charging damage in PMOSFETs , 2002, IEEE Electron Device Letters.

[8]  Andreas Martin Review on the reliability characterization of plasma-induced damage , 2009 .

[9]  W. Lin,et al.  Multiple-terminal gate charging effect - competing/compensating charging behavior , 2003, IEEE Electron Device Letters.

[10]  Andreas Martin,et al.  MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology , 2010, 2010 IEEE International Integrated Reliability Workshop Final Report.

[11]  J. Gambino,et al.  Ultra-thin Gate Dielectric Plasma Charging Damage in SOI Technology , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[12]  M. Bidaud,et al.  Ultra-Thin Gate Oxide (1.6 nm): New Mechanisms of Plasma Induced Damage and Oxidation Process Optimisation , 2000, 30th European Solid-State Device Research Conference.

[13]  Andreas Martin,et al.  An introduction to fast wafer level reliability monitoring for integrated circuit mass production , 2004, Microelectron. Reliab..

[14]  Terence B. Hook,et al.  Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation , 2001, Microelectron. Reliab..