Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System

The purpose of this paper is to present a methodology and tools for the design and test of an EN298 compliant ASIC chip for a safety-critical gas burner control system. Safe operation, as far as the critical variable is concerned, is guaranteed in the presence of two simultaneous faults. Emphasis is put on circumventing methodology, EDA (Electronic Design Automation) and foundry limitations and on product certification requirements.

[1]  João Paulo Teixeira,et al.  Defect level evaluation in an IC design environment , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  João Paulo Teixeira,et al.  Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems , 1999, J. Electron. Test..

[3]  João Paulo Teixeira,et al.  Defect-oriented test quality assessment using fault sampling and simulation , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[4]  João Paulo Teixeira,et al.  Defect-oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[5]  Edward J. McCluskey,et al.  Stuck-fault tests vs. actual defects , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[6]  Edward J. McCluskey,et al.  Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[7]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[8]  Edward J. McCluskey,et al.  Finite state machine synthesis with concurrent error detection , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[9]  藤原 秀雄,et al.  Logic testing and design for testability , 1985 .

[10]  Niraj K. Jha,et al.  Design and synthesis of self-checking VLSI circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  M.B. Santos,et al.  Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[12]  M. Ray Mercer,et al.  On the decline of testing efficiency as fault coverage approaches 100% , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[13]  Niraj K. Jha,et al.  Design and Synthesis of Self-Checkmg VLSI Circuits , 1993 .

[14]  Marcelo Lubaszewski,et al.  Reliable fail-safe systems , 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).

[15]  Cecilia Metra,et al.  Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults , 1995, J. Electron. Test..

[16]  Niraj K. Jha,et al.  Testing and Reliable Design of CMOS Circuits , 1989 .

[17]  Michael Nicolaidis.  Fault secure property versus strongly code disjoint checkers , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  John F. Wakerly,et al.  Error detecting codes, self-checking circuits and applications , 1978 .