Low power and high-speed analog CDMA matched filters have been developed based on the floating-gate MOS technology. As compared to our previous approach (A. Okada and T. Shibata, Proc. IEEE ISCAS, vol. 2, pp. II-392-II-395), the power dissipation in sample/hold circuits has been reduced by employing the single-step matching scheme. In addition, the number of capacitors involved in the matching calculation is decreased by reconsidering the matching algorithm. As a result, 85% power reduction in a matching cell has been achieved in the present work. Furthermore, the introduction of the pseudorandom noise (PN) code-shifting scheme has eliminated the necessity of analog shift resistors for synchronization, thus enabling simple and more accurate circuit operation. The total CDMA matched filter circuits were designed, laid out, and their operation was confirmed by HSPICE simulation. The key circuits in the system were fabricated in a preliminary run and their characteristics were evaluated for the total circuit design.
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