SET and RESET pulse characterization in BJT-selected phase-change memories

This paper presents program pulse characterization in an 8-Mb BJT-selected phase-change memory test chip. Experimental results of the impact of the bit-line resistance over programming pulse efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

[1]  Byung-Gil Choi,et al.  Phase-Transition Random-Access Memory (PRAM) , 2004 .

[2]  S. Hudgens,et al.  Nonvolatile, high density, high performance phase-change memory , 2000, 2000 IEEE Aerospace Conference. Proceedings (Cat. No.00TH8484).

[3]  B. Vajdic,et al.  A 90-ns one-million erase/program cycle 1-Mbit flash memory , 1989 .

[4]  G. Torelli,et al.  Bit-Line Biasing Technique for Phase-Change Memories , 2004 .

[5]  T. Lowrey,et al.  Ovonic unified memory - a high-performance nonvolatile memory technology for stand-alone memory and embedded applications , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[6]  R. Bez,et al.  An 8Mb demonstrator for high-density 1.8V Phase-Change Memories , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[7]  G. Torelli,et al.  An improved method for programming a word-erasable EEPROM , 1983 .