CPU Testability in Embedded Systems
暂无分享,去创建一个
[1] Nektarios Kranitis,et al. Directed Random SBST Generation for On-Line Testing of Pipelined Processors , 2008, 2008 14th IEEE International On-Line Testing Symposium.
[2] Eric Rotenberg,et al. Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).
[3] SAEED SHAMSHIRI,et al. Instruction-level test methodology for CPU core self-testing , 2005, TODE.
[4] Jacob A. Abraham,et al. Automated mapping of pre-computed module-level test sequences to processor instructions , 2005, IEEE International Conference on Test, 2005..
[5] Paolo Bernardi,et al. On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores , 2007, 12th IEEE European Test Symposium (ETS'07).
[6] Yervant Zorian,et al. Application and analysis of rt-level software-based self-testing for embedded processor cores , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[7] M. Hatzimihail,et al. A methodology for detecting performance faults in microprocessors via performance monitoring hardware , 2007, 2007 IEEE International Test Conference.
[8] Nikil D. Dutt,et al. Functional coverage driven test generation for validation of pipelined processors , 2005, Design, Automation and Test in Europe.
[9] E. Sanchez,et al. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies , 2007, 2007 Eighth International Workshop on Microprocessor Test and Verification.
[10] A. Desai,et al. Architecture Independent Characterization of Embedded Java Workloads , 2009, IEEE Computer Architecture Letters.
[11] Yu Hu,et al. The design-for-testability features of a general purpose microprocessor , 2007, 2007 IEEE International Test Conference.
[12] Hideo Fujiwara,et al. Efficient template generation for instruction-based self-test of processor cores , 2004, 13th Asian Test Symposium.
[13] Kwang-Ting Cheng,et al. On a software-based self-test methodology and its application , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).
[14] Janusz Sosnowski. Software-based self-testing of microprocessors , 2006, J. Syst. Archit..
[15] Giovanni Squillero,et al. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[16] Michail Maniatakos,et al. Systematic Software-Based Self-Test for Pipelined Processors , 2008, IEEE Trans. Very Large Scale Integr. Syst..
[17] Hideo Fujiwara,et al. Instruction-based delay fault self-testing of processor cores , 2004, 17th International Conference on VLSI Design. Proceedings..
[18] Charles E. Stroud. A Designer's Guide to Built-In Self-Test , 2002 .