A Methodology for Transistor-Efficient Supergate Design

The number of transistors required for the implementation of a logic function is a fundamental consideration in digital VLSI design. While the determination of a series-parallel implementation can be straightforward once a simplified Boolean expression of the function is available, this may not be an optimum solution. In this paper, a methodology is developed for minimizing the number of transistors that starts from a sum-of-products expression and utilizes non-series-parallel structures. Experimental results demonstrate the efficiency of the approach

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