Problem statement: Verification of correct functionality of semiconductor devices has been a challenging problem. Given the device fabrication cost, it is critical to verify the expected functionality using simulations of executable device models before a device manufactured. However, typical industrial scale devices today involve large number of interactions between their components. Complexity of verifying all interactions becomes almost intractable even in simulation. The infeasible interactions need to be eliminated from verification consideration in order to reduce the complexity of the problem. Also an empirical metric of completeness of the verification of such interactions is needed. This metric should provide measure of quality of verification as well as that of degree of confidence in future correct behavior of the device. Metric should guide stimulus generation for simulation so that all aspects of the device functionality can be covered in verification. Existing coverage metrics focus almost exclusively on verification of individual components. Approach: In this study, interactions between device components modeled as independent processes, were considered. The interactions considered between control flow paths in different processes. Present algorithm analyzed the dependency between the control flow paths. It was also determined set of feasible interactions between the control flow paths and pruned out the infeasible ones. Remaining set of feasible interactions constituted our interaction coverage metric. Our metric handled device designs with an arbitrary number of processes. Results: Number of interactions to be considered in simulation-based verification was significantly reduced by our coverage metric using our proposed algorithms. This limited the complexity and scope of stimulus generation to coverage of only set of feasible interactions. Conclusion: Proposed coverage metric was able to provide realistic measure of degree of verification of components interactions as well as effectively guide the test generation process for device designs consisting of an arbitrary number of components.
[1]
I.G. Harris,et al.
An efficient control-oriented coverage metric
,
2005,
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[2]
Jacob A. Abraham,et al.
Abstraction Techniques for Validation Coverage Analysis and Test Generation
,
1998,
IEEE Trans. Computers.
[3]
Sigrid Eldh.
Software Testing Techniques
,
2007
.
[4]
Boris Beizer,et al.
Software testing techniques (2. ed.)
,
1990
.
[5]
Maciej J. Ciesielski,et al.
Functional verification and simulation of FSM networks
,
1993,
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.
[6]
Anneliese Amschler Andrews,et al.
On statistical behavior of branch coverage in testing behavioral VHDL models
,
2000,
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).
[7]
Ian G. Harris,et al.
Fault models and test generation for hardware-software covalidation
,
2003,
IEEE Design & Test of Computers.
[8]
Kurt Keutzer,et al.
Coverage Metrics for Functional Validation of Hardware Designs
,
2001,
IEEE Des. Test Comput..
[9]
Ian G. Harris,et al.
A Coverage Metric for the Validation of Interacting Processes
,
2006,
Proceedings of the Design Automation & Test in Europe Conference.
[10]
Nadeem Malik,et al.
Automaton: an autonomous coverage-based multiprocessor system verification environment
,
1997,
Proceedings 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype.
[11]
Kwang-Ting Cheng,et al.
A functional fault model for sequential machines
,
1992,
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12]
Kurt Keutzer,et al.
An observability-based code coverage metric for functional simulation
,
1996,
Proceedings of International Conference on Computer Aided Design.
[13]
Giovanni Squillero,et al.
RT-Level ITC'99 Benchmarks and First ATPG Results
,
2000,
IEEE Des. Test Comput..