N5 BEOL Process Options Patterning flows Comparing 193immersion to Hybrid EUV or Full EUV

The foundry N5 node requires 16nm half-pitch interconnects for the advanced logic BEOL. Imec has evaluated on testchip vehicles different integration approaches : 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization) . Four different patterning combinations have been evaluated to reach this scaling to dual damascene. In this paper, we will compare these process flows and link them to their wafer cost and then recommend a best option.