Optimally matched current mirror layout pattern generation using genetic optimization
暂无分享,去创建一个
[1] K. R. Lakshmikumar,et al. Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .
[2] Yingtao Jiang,et al. An automated design tool for analog layouts , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Sam Kwong,et al. Genetic algorithms: concepts and applications [in engineering design] , 1996, IEEE Trans. Ind. Electron..
[4] M.J.M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .
[5] Günhan Dündar,et al. New layout generator for analog CMOS circuits , 2007, 2007 18th European Conference on Circuit Theory and Design.
[6] Chang Wook Ahn,et al. A genetic algorithm for shortest path routing problem and the sizing of populations , 2002, IEEE Trans. Evol. Comput..
[7] Shyh-Chang Lin,et al. A Matching-based Placement and Routing System for Analog Design , 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
[8] Jing Li,et al. Structured analog circuit design and MOS transistor decomposition for high accuracy applications , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[10] E. Felt,et al. Measurement And Modeling Of MOS Transistor Current Mismatch In Analog IC's , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[11] Nuno Horta,et al. LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Randall L. Geiger,et al. A new current mirror layout technique for improved matching characteristics , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).
[13] Günhan Dündar,et al. Analog Layout Generator for CMOS Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.